Microcontroller ARMv8-A 64-bit Architecture Training

• What is Calling conventions?
• What are Neon and Floating point?
• What are Debug and Power management?
• What is ARM architecture (ARMv8.x-A and ARMv9.x-A-A)?
• What is support for the execution of 32-bit ARMv7-A code?
• How to work with Exception, Interrupt handling, and the Exception Levels?
• What is TrustZone overview (Secure monitor at Exception Level 3 plus secure world)?
• What is 64-bit ISA (registers, instruction set, system instructions, etc)?
• How to work with the Memory model and paging?

• 32 Hrs. Instructor-led Online Training
• Recorded Videos After Training
• Digital Learning Material
• Course Completion Certificate
• Lifetime e-Learning Access
• 24x7 After Training Support

• Software Developers
• System Architects who develop Cortex-A53, Cortex-A57, and other ARMv8-A processors

• You are supposed to carry basic knowledge of ARM 32-bit v7 Architecture and general computer architecture to pursue this Microcontroller ARMv8-A 64-bit Architecture Training.

Module 1: Introduction to ARM 64-bit Architecture

Module 2: ARM architecture profiles, what is v8-A and the other architecture profiles

Module 3: ARM architecture extensions to v8-A, the v8.1A, v8.2-A, etc and v9-A

Module 4: v8-A introduction and rational

Module 5: Support for v7 legacy code

• AArch32 and AArch64 state
• v7 instruction set changes
• Deprecation
• Additional features (some new 64-bit features have also been added as new features available to 32-bit execution)

Module 6: 64-bit platform architecture overview

• Sample SoC
• MP Core
• Interconnect (ACE or CHI)
• Coherency and the interconnect
• Distributed interrupt controller
• Role of firmware
• Booting

Module 7: A64 ISA

Module 8: Integer registers

Module 9: Instruction set

• Integer operations
• Memory operations
• Stack
• System instructions
• System control registers
• Relationship to v7 support and co-processors
• Calling conventions
• Memory access (DRAM and device)
• Ordering model
• Barriers
• Semaphores
• Cache management
• Floating point, advanced SIMD, crypto
• Registers and instructions

Exception levels

• The 4 exception levels
• Stack model, handler and thread
• Vector table
• Core implementation choices
• Switching AArch32 and AArch64 state

Exception and interrupt handling

• Control of delivery of exceptions and interrupts
• Syndrome registers
• Switching exception levels
• Return from exception

Paging

• Memory management with page tables
• 4K, 16K and 64K granules
• Page sizes
• Features achieved with page tables, such as execute never
• Address space trickery – fields in pointers that are not part of the address, such as tags and pointer authentication
• TLB management

Module 10: EL2 Overview

• Processor features intended for virtualization
• Use of exception levels
• Memory management
• Second level page tables
• Memory partitioning
• I/O MMU (SMMU)
• The use of EL2 for UEFI execution during boot
• Addition of Secure EL2 to the architecture

Module 11: Caches

• Hardware cache coherency
• Software responsibilities
• Cache control in software
• Security (TrustZone)
• TrustZone functionality

Module 12: Secure memory

• Links to TrustZone in other architectures
• 32-bit or 64-bit TrustZone
• Implications on exception levels, and the addition of secure EL2
• Switching bitness of TrustZone
• Dynamic TrustZone, also called Realms, is part of ARM’s Confidential Computer Architecture

Module 13: Other topics

• Core power management, external power controller
• Power modes (dormant, shutdown)
• WFI, WFE, SEV
• Debug (hardware and software based debug)
• RAS – Reliability, Availability, Serviceability
• Boot process