VERILOG HDL Training

• Elucidate the significance and process of VLSI
• Use advanced digital design components to build a logical design
• Work with data types, looping, level of abstraction, and different types of programing in Verilog HDL
• Learn compiler directives and CMOS gate modeling
• Write reusable code for synthesis of Verilog

• Final year engineering and IT graduate students
• Professionals switching to VLSI design domain

Module 1: Introduction to VLSI

Module 2: Advanced Digital Design

1. Combination Device

• Adders
• Subtractor
• Mux/Demux
• Encoder/Decoder
• Parity checker/generator

2. Sequential Device

• Flip Flops
• Latchs
• Register Application
  • Shifters
  • Counters
• Memory
  • RAM
  • SRAM
  • ROM

3. Logic Implementation

• Using FSM
• Logic Mapping

Module 3: Verilog HDL

1. Introduction HDL's

• Introduction to HDL's (Verilog)
• Introduction to Design Levels

2. Data Types

• Pre-defined Data Types
• User Defined Data Type
• Data Conversion

3. Levels of abstraction

4. Primitive Programming

• Introduction to Primitive Programming
• Module, Ports types Declaration
• Identifiers
• Primitives List
• Use of Primitive

5. Data Flow Programming

• Introduction to Data Flow Programming
• Operators
• Use of Operators
• When Statements , Data Flow designing

6. Behavioral Programming

• Introduction to Behavioral Programming
• Always Block
• Blocking and Non-blocking statements
• Control statements
• If -else statements
• Case Statement

7. State Machine designing

11. Memory Designing

• RAM Designing
• ROM Designing

8. Function & TASK

9. System Tasks

10. Behavioral Modeling

• Interfacing method

11. Verification

• Delay Model
• Initial Block
• Fork -Join
• Test Bench
• Timing checks
• Assertion based verification

12. Looping

• For
• While
• Repeat
• Forever
• Wait

13. UDP

14. Compiler Directives

15. CMOS Gate Modeling

Module 4: Synthesis of Verilog

• Code for synthesis
• Writing reusable code

Module 5: Project Software Package

• ModelSIM
• Xilinx